1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a fully-hidden refresh DRAM (Dynamic Random Access Memory) capable of fully hiding an internally performed refreshing operation from an outside. More particularly, the present invention relates to a dynamic semiconductor memory device having an interface fully compatible with an SRAM (Static Random Access Memory).
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is in general constructed from memory cells each constituted of one transistor and one capacitor. Therefore, an occupation area of the memory cell is small and DRAM is suited for implementation of a large capacity memory device. The DRAM, however, stores information in a capacitor in the form of electric charges and electric charges accumulated in the capacitor leak out over time to cause destruction of data. Therefore, in order to prevent the destruction of data due to leakage of the electric charges, it is required to perform a refreshing operation of re-writing storage data periodically. In a normal operation mode of performing a data access, an external memory controller controls timings for executing the refreshing.
An SRAM (Static Random Access Memory) is constructed from memory cells each constituted of 4 transistors and 2 load elements and an occupation area of a memory cell is larger as compared with a DRAM cell. An SRAM cell is constructed basically from a flip-flop and stores data as far as power is supplied, and therefore, no requirement arises for refreshing in SRAM. Thus, in general, SRAM is used as a main memory in portable equipment because of controllability.
In the field of portable equipment as well, it is increasingly required to handle a great volume of data such as image data due to improvement in functionality, and accordingly the main memory device is required to have an adequately large storage capacity. If such a large capacity memory device is constructed using an SRAM, an occupation area of the memory would be increased, to be a great obstacle against down-sizing of the entire system.
Thus, a hidden refresh DRAM requiring no external refresh control has been proposed for a main memory device of a large storage capacity as substitution for the SRAM. In such a hidden refresh DRAM, a refresh request is repeatedly issued internally at prescribed intervals to perform refreshing operations internally in accordance with the refresh requests. When external data access conflicts with an internal refresh request, the external data access or the internal refresh request, whichever is designated at a faster timing, is performed by an arbitration circuit. For example, in a case where a refresh request is supplied faster in timing than data access (data writing or data reading), a refreshing operation is first performed, and after completion of the refreshing operation, a data access operation is performed in accordance with the external data access.
In such a fully-hidden refresh DRAM is called a VSRAM (Virtually Static RAM). An example of such a memory is disclosed in, for example, “A 30 μA Data-Retention Pseudo-static RAM with Virtually Static RAM Mode” by SAWADA et. al. IEEE Journal of Solid State Circuits, Vol. 23, No. 1, pp. 12 to 17.
In a fully hidden refresh DRAM which does not require an external refreshing control to completely hide a refreshing operation from outside, refresh requests are issued using a built-in timer circuit and refresh is performed in accordance with a refresh address generated internally in accordance with the refresh request. The refresh timer operates asynchronously with external data access, and a necessity arises for arbitration between a refresh request and a data access instruction since data destruction occurs when an external data access and a refresh request conflict with each other.
As an arbitration circuit, in the above prior art reference, a flip-flop is employed that receives a normal access request responsive to a chip enable signal /CE and a refresh request generated internally, and it is determined which of the requests is activated earlier. In this prior art, the determination circuit is constructed of a NAND type flip-flop. Therefore, when a refresh request and a data access request conflict with each other, in order to consecutively perform refreshing operation and data access operation, the following condition is imposed: even if a signal instructing one request enters an inactive state, the other signal instructing the other request is required to be maintained in active state. For this reason, an activation period of a refresh request is made longer than a period for which a refreshing operation is performed internally, and an activation period of a data access request signal is also required to be made longer than a period for which the refreshing operation is performed and completed. Hence, in an external data access, for example a command instructing a data access request cannot be applied in a one-shot pulse form in synchronization with a clock signal.
Furthermore, in this prior art, if a data access request is issued when an internal state transitions to a precharging operation state after a refreshing operation is completed in accordance with a refresh request, the external data access request is accepted to start an internal operation starts. Therefore, there is a possibility that the data access operation is started before an internal circuit does not restore completely to a prescribed initial state, and correct data access operation could not ensured.
If a refresh request is issued when a normal data access request is deactivated and a precharge operation is being internally performed, a similar problem arises.
In the above prior art reference, a data access request is activated in accordance with chip enable signal /CE. Therefore, such a prior art technique has a problem that it can not be applied to an interface utilizing an address transition detection signal generally widely adopted as an interface of the SRAM. That is, in the above document, the chip enable signal is required to be toggled depending on data access and it is impossible to change an address signal with chip enable signal /SE fixed at L level, to define a memory cycle in accordance with the transition of the address signal. Therefore, the prior art technique could not accommodate for an interface of an address transition detection type, thereby disabling implementation of a DRAM having complete compatibility with an SRAM.
In a case where data accesses are consecutively performed, according to the configuration of the above prior art document; the data accesses are consecutively accepted. In this prior art document, a word line is driven to an inactive state automatically when a prescribed time elapses after the word line is selected and driven into an active state. In a case where the next data access instruction is supplied before the prescribed time elapses, the next data access operation is performed prior to restoration of internal circuitry to a precharged state, data collision may occur to cause a problem of correct data access being not ensured.